1. TECHNICAL FIELD
The present invention relates generally to the field of semi-conductor manufacturing and, more specifically, to a method for forming field effect transistors with selective threshold voltages.
2. BACKGROUND ART
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in the design and fabrication of field effect transistors (FETs), such as those used in CMOS technologies. FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.) One of the fundamental parameters of the of FET design is the threshold voltage (V.sub.T). The threshold voltage of a FET is defined as the gate voltage required to switch the transistor on or off depending on the type of transistor. In particular, enhancement mode FETs are normally off until a voltage equal to the threshold voltage is applied to the gate, forming a conducting channel under the gate which turns on the FET. By contrast, depletion mode FETs are normally on until a voltage equal to the threshold voltage (usually a negative voltage) is applied to gate which depletes the conductive channel and turns the FET off. In either case the threshold voltage of the FET is a important parameter and significantly controls the behavior of the FET.
Most integrated devices made today include thousands, if not millions of FETs on a single chip. In many cases it is desirable to make the individual FETs on a chip have different threshold voltages such that the different FETs switch at different times. Additionally, it is desirable to be able to change FET's from enhancement mode to depletion mode and vice versa to give additional flexibility to device designers.
The threshold voltage of a FET is determined primarily by the implant dose in the channel and the gate dielectric thickness. Present methods for providing FETs with different threshold voltages on the same chip require a different masking step followed by a specialized channel implant for each different threshold voltage desired. Thus, a chip that requires FETs with five different threshold voltages requires five different masking steps, each followed by a specialized implant of varying dose and energy designed to adjust the threshold voltage. This greatly increases the process complexity with the attending problems, all of which serve to drive chip yield down and costs up.
Thus, there was a need for an improved method for fabricating field effect transistors with varying threshold voltages that does not require excessive masking steps.